Integrated circuits frequently contain multiple clock domains whose clocks are generated from different reference clock input pins. Where the relative phases of the domain clocks and the reference clocks are not controlled, the clocks are asynchronous. Transitions on signals which cross between asynchronous clock domains may be received on random clock cycles, which can lead to digital behavior which, while correct (conforming to the specification for the design), may be nondeterministic (that is, not predictable or easily repeatable). Nondeterminism can be detrimental to silicon debug and manufacturing test techniques employing test equipment which stores a unique expected response for each input test pattern. Fault-free dice which produce a response which is correct but which differs from the stored expected response may be rejected, leading to unnecessary yield loss. Tests which are designed to be insensitive to nondeterminism often have lower quality, which can lead to faulty dice which are not rejected by the test and thus can reduce outgoing product quality. One approach is to enforce deterministic behavior by controlling the relative timing of the edges of the clocks during testing. Historically, it has been relatively easy to devise reference clock timings that achieve determinism across a range of process, voltage, and temperature variations. However, it is believed that such clock alignments are becoming relatively more difficult to achieve reliably due to increasing clock frequencies and process technology advances, which can increase the variability of the device characteristics and reduce the accuracy of pre-silicon simulation.
Existing techniques for characterizing the timing relationship between two internal signals, such as two clock signals or a clock and a data signal, for example, are increasingly insufficiently accurate to facilitate post-silicon debug operations or are increasingly insufficiently rapid for testing during manufacturing. As a result, design or manufacturing efficiency may be adversely affected.
One example of a presently used signal measurement technique uses laser voltage probing. Such laser probe measurements can consume several days and involve chip de-cap or special fine silicon preparation, which can potentially change or even destroy circuit behavior. This technique is frequently not readily repeatable on a large sample population of products.
Domain-crossing signals may also be observed through an external interface. However, systematic and random delay mismatches in the internal multiplexer tree and input/output circuitry through which the signals pass en route to the external interface may make the relative timing between the signals at the chip pins differ substantially from that at the sources of the signals, limiting the resolution or accuracy of the technique.
Yet another approach is the use of a characterization test which is specifically designed to pass when the internal signals are properly aligned and fail when they are not. With this technique, there is the possibility that a phenomenon not related to the clock domain crossings can influence the observed results. This method typically does not provide actual skew measurements for domain-crossing signals, but merely a passing region of skew control settings instead.